Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect

机译：错位对0.18u多级互连集成的影响的研究

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process tod emand a more stringent control over the in-line parameter. For multilevel interconnect, each processing step inthe formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even mor echallenging as mor elayers of interconnect are required to meet the speed performance and density requirements.

机译：随着技术随着越来越严格的设计规则而不断缩小，集成过程不可避免地要求对在线参数进行更严格的控制。对于多层互连，形成通孔插塞和金属互连的每一层的每个处理步骤都会影响硅晶片的整体性能和良率。由于需要更多的互连层以满足速度性能和密度要求，因此对过程的控制变得更加困难。

著录项

来源
《Conference on Challenges in Process Integration and Device Technology 18-19 September 2000 Santa Clara, USA》|2000年|p.99-106|共8页
会议地点 Santa Clara CA(US)
作者
Teck Jung Tang; Juan Boon Tan; Sajan Markkey; Tae Jong Lee; Alan Cuthbertson;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
0.18um; Misalignment; Integration; Multilevel; Interconnect; W-plug corrosion;

机译：0.18um;错位；积分;多层次互连； W塞腐蚀;

相似文献

外文文献
中文文献
专利

1. Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI) [J] . Venkatesan R., Davis J.A., Bowman K.A., IEEE transactions on very large scale integration (VLSI) systems . 2001,第6期

机译：千兆级集成（GSI）的最佳n层多层互连架构
2. Effects of Deposition Temperature on Low-Dielectric Fluorinated Amorphous Carbon Films for Ultralarge-Scale Integration Multilevel Interconnects [J] . Sung-Hoon Yang, Jeongwon Park, Jung-Yeul Kim, Microchemical Journal: Devoted to the Application of Microtechniques in all Branches of Science . 1999,第1期

机译：沉积温度对超大规模集成多级互连低介电氟化非晶碳膜的影响
3. The impacts of city-specific factors on social integration of Chinese migrant workers: A study using multilevel modeling [J] . Tian Ming, Tian Zheng, Sun Wei Journal of urban affairs . 2019,第3期

机译：城市特定因素对中国农民工社会融合的影响：基于多层次模型的研究
4. Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect [C] . Teck Jung Tang, Juan Boon Tan, Sajan Markkey, Conference on challenges in process integration and device technology . 2000

机译：未对准对0.18U多级互连集成中的错位影响
5. Multilevel interconnect architectures for gigascale integration (GSI). [D] . Venkatesan, Raguraman. 2003

机译：用于千兆级集成（GSI）的多层互连体系结构。
6. Integrating Space with Place in Health Research: A Multilevel Spatial Investigation Using Child Mortality in 1880 Newark New Jersey [O] . Hongwei Xu, John R. Logan, Susan E. Short -1

机译：在健康研究中将空间与位置整合：1880年使用儿童死亡率进行的多层次空间调查新泽西州纽瓦克
7. Low Cost 3D Multilevel Interconnect Integration for RF and Microwave Applications [O] . Ayad Ghannam, David Bourrier, Lamine Ourak, 2015

机译：用于射频和微波应用的低成本3D多级互连集成
8. Fabrication and Electrical Characterization of Multilevel Aluminum Interconnects Used to Achieve Silicon-Hybrid Wafer-Scale Integration [R] . Takahashi, G. L. 1987

机译：用于实现硅混合晶圆级集成的多层铝互连的制作和电气特性

Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect

摘要

著录项

相似文献

相关主题

期刊订阅