Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect

机译：未对准对0.18U多级互连集成中的错位影响

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As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process tod emand a more stringent control over the in-line parameter. For multilevel interconnect, each processing step inthe formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even mor echallenging as mor elayers of interconnect are required to meet the speed performance and density requirements.

机译：随着技术继续与更严格的设计规则缩小，对于集成过程TOD，它变得不可避免地是对在线参数的更严格控制。对于多级互连，每个处理步骤的每个通过插头和金属互连的形成每个层都会影响硅晶片的整体性能和产量。因此，对该过程的控制变得甚至是MoreChallenging，因为Mor Elayers的互连需要满足速度性能和密度要求。

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《Conference on challenges in process integration and device technology》|2000年||共8页
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Teck Jung Tang; Juan Boon Tan; Sajan Markkey; Tae Jong Lee; Alan Cuthbertson; SPIE-The International Society for Optical Engineering;
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中图分类半导体技术;
关键词
0.18um; Misalignment; Integration; Multilevel; Interconnect; W-plug corrosion;

机译：0.18um;未对准;集成;多级;互连;W-plug腐蚀;

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1. Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI) [J] . Venkatesan R., Davis J.A., Bowman K.A., IEEE transactions on very large scale integration (VLSI) systems . 2001,第6期

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2. Effects of Deposition Temperature on Low-Dielectric Fluorinated Amorphous Carbon Films for Ultralarge-Scale Integration Multilevel Interconnects [J] . Sung-Hoon Yang, Jeongwon Park, Jung-Yeul Kim, Microchemical Journal: Devoted to the Application of Microtechniques in all Branches of Science . 1999,第1期

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4. Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect [C] . Teck Jung Tang, Juan Boon Tan, Sajan Markkey, Conference on Challenges in Process Integration and Device Technology 18-19 September 2000 Santa Clara, USA . 2000

机译：错位对0.18u多级互连集成的影响的研究
5. Multilevel interconnect architectures for gigascale integration (GSI). [D] . Venkatesan, Raguraman. 2003

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8. Fabrication and Electrical Characterization of Multilevel Aluminum Interconnects Used to Achieve Silicon-Hybrid Wafer-Scale Integration [R] . Takahashi, G. L. 1987

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Investigation on the Impacts of Misalignment in the Integration of 0.18u multilevel Interconnect

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