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Killer defects caused by localized sub-100-nm critical dimension reticle errors

机译:局域性的100 nm以下临界尺寸标线片错误导致的杀手级缺陷

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Abstract: For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques (phase shifting, optical proximity correction, etc.) have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k$-1$/ factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k$-1$/ factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50 nm and smaller can cause unacceptable wafer CD variation. Current high end reticle manufacturers are capable of meeting a total CD uniformity specification of approximately 40 nm as measured by sampling strategies using optical metrology tools. These tools are very useful for detecting macro changes in CD; however, they will only detect a localized error if it happens to occur precisely at the point of measurement. In contrast, a pattern inspection system employing a linewidth measurement algorithm can ensure detection of all localized errors within the detection and review capability of the system. The problem with reticle CD error detection capability is that there is a large discrepancy between currently available detection of greater than or equal to 150 nm and required detection of less than or equal to 50 nm necessary for proper wafer functionality at low k$-1$/ lithography. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programmed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of less than or equal to 100 nm reticle defects. !1
机译:摘要:出于明显的成本原因,半导体制造商一直在努力利用当前安装的晶圆步进机来生产尺寸越来越小的晶圆。已经成功地使用了许多技术(相移,光学邻近校正等)来从这些步进器中“压缩”更多的分辨率,这比以前认为的要多。使用非侵略性k $ -1 $ /因素处理的晶圆在掩模和晶圆特征尺寸之间提供了线性相关性。然而,已经表明将k $ -1 $ /因子推至非常低的水平会导致光掩模和晶片临界尺寸的变化之间的非线性响应。这种非线性要求非常严格的光掩模CD控制规范。总的CD误差为50 nm或更小会导致不可接受的晶圆CD变化。当前的高端掩模版制造商能够满足大约40 nm的总CD均匀性规格,这是通过使用光学计量工具的采样策略测得的。这些工具对于检测CD的宏变化非常有用。但是,只有在恰好发生在测量点的情况下,他们才会检测到局部误差。相反,采用线宽测量算法的图案检查系统可以确保在系统的检测和检查功能范围内检测到所有局部错误。掩模版CD错误检测功能的问题在于,当前可用的大于或等于150 nm的检测与所需的小于或等于50 nm的检测之间存在很大差异,以低k-1的正常晶圆功能/光刻。在本文中,测试了一种新的高级线测量算法的缺陷敏感性和错误检测性能。测试工具包括行业标准和定制设计的编程缺陷测试模板。另外,分析了具有自然发生的局部CD错误并导致晶片图案桥接的生产掩模。这种新的实验算法已显示了小于或等于100 nm标线缺陷的局部CD错误检测。 !1

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