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首页> 外文会议>Physics, Simulation, and Photonic Engineering of Photovoltaic Devices VIII >A Porous Ge/Si Interface Layer for Defect-free Ⅲ-Ⅴ Multi-Junction Solar Cells on Silicon
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A Porous Ge/Si Interface Layer for Defect-free Ⅲ-Ⅴ Multi-Junction Solar Cells on Silicon

机译：硅上无缺陷的Ⅲ-Ⅴ多结太阳能电池的多孔Ge / Si界面层

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摘要

Ⅲ-Ⅴ solar cell cost reduction and direct Ⅲ-Ⅴ/Si integration can both be realized by depositing a thinlayer of high-quality Ge on relatively low-cost Si substrates. However, direct epitaxial growth of Geon Si substrates is difficult due to the 4% lattice mismatch between the film and the substrate.Threading dislocations (TDs) introduced within the Ge layer have a detrimental effect on deviceperformances. The goal of this research is to address the perennial need to minimize the defect densityof Ge epilayers grown on a Si substrate. We seek to accommodate the effects of the lattice mismatchby introducing a porous Si interface layer to intercept dislocations and prevent them from reaching theactive layers of the device. The porous Si layer is formed through dislocation-selectiveelectrochemical deep etching and thermal annealing. The porous layer created beneath the top Ge layercan both act as dislocation traps and as a soft compliant substrate, which displays high flexibility.Transmission electron microscopy (TEM) analysis of the Ge/porous Si interface shows that the latticemismatch strain of the Ge films was almost relaxed. The surface roughness of this modified Ge/Sisubstrate has been reduced using chemical mechanical polishing (CMP) process to fulfil therequirements for epitaxy of Ⅲ-Ⅴ alloys. Finally, we present simulation results exploring the effect ofthreading dislocations on device performance.
机译：可以通过在相对低成本的Si衬底上沉积高质量Ge的薄层来实现Ⅲ-Ⅴ太阳能电池成本的降低和Ⅲ-Ⅴ/ Si直接集成。然而，由于薄膜和衬底之间的4％晶格失配，很难实现Ge \ r \非Si衬底的直接外延生长。\ r \ n在Ge层中引入的螺纹位错（TD）对器件有不利影响\ r \ n表演。这项研究的目的是解决长期以来的需要，以最小化在Si衬底上生长的Ge外延层的缺陷密度。我们试图通过引入多孔Si界面层来拦截位错并防止其到达器件的有源层，以适应晶格失配的影响。多孔硅层是通过位错选择性电化学深蚀刻和热退火形成的。在顶部Ge层下方形成的多孔层既可以用作位错陷阱，又可以用作柔软的柔性基底，显示出很高的柔韧性。\ r \ n对Ge /多孔Si界面的透射电子显微镜（TEM）分析表明Ge薄膜的晶格\ r \ nmismatch应变几乎放松。通过化学机械抛光（CMP）工艺可以降低这种改性的Ge / Si \ r \ n衬底的表面粗糙度，从而满足Ⅲ-Ⅴ合金外延的要求。最后，我们提供仿真结果，探讨\ r \ n线程错位对设备性能的影响。

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  • 会议地点 0277-786X;1996-756X
  • 作者

    Youcef A. Bioud; Meghan N. Beattie; Abderraouf Boucherif; Mourad Jellit; Romain Stricher; Serge Ecoffey; Gilles Patriarche; David Troadec; Ali Soltani; Nadi Braidy; Matthew Wilkins; Christopher E. Valdivia; Karin Hinzer; Dominique Drouin; Richard Ares;

  • 作者单位

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    SUNLAB, Centre for Research in Photonics, University of Ottawa, Ottawa, Ontario, K1N 6N5, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Centre for Nanoscience and Nanotechnology, CNRS, Universite Paris-Sud, Universite Paris-Saclay, Route de Nozay, 91460 Marcoussis, France;

    Universite Lille, CNRS, Centrale Lille, ISEN, Universite Valenciennes, UMR 8520 - IEMN, F-59000 Lille, France;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    SUNLAB, Centre for Research in Photonics, University of Ottawa, Ottawa, Ontario, K1N 6N5, Canada;

    SUNLAB, Centre for Research in Photonics, University of Ottawa, Ottawa, Ontario, K1N 6N5, Canada;

    SUNLAB, Centre for Research in Photonics, University of Ottawa, Ottawa, Ontario, K1N 6N5, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

    Laboratoire Nanotechnologies Nanosystemes (LN2)-CNRS UMI-3463, Institut Interdisciplinaire d’Innovation Technologique (3IT), Universite de Sherbrooke, Sherbrooke, Quebec, Canada;

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