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首页> 外文期刊>IEEE transactions on electronics packaging manufacturing >Correlation of flip chip underfill process parameters and material properties with in-process stress generation
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Correlation of flip chip underfill process parameters and material properties with in-process stress generation

机译：倒装芯片底部填充工艺参数和材料性能与过程中应力的相关性

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摘要

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing.
机译：电子包装设计正朝着更少的包装水平发展，以实现小型化并提高电子产品的性能。一种这样的封装设计是板上倒装芯片（FCOB）。在这种方法中，将芯片面朝下直接连接到印刷线路板（PWB）。由于封装由不同的材料组成，由于芯片，PWB和互连材料之间的热膨胀系数（CTE）不匹配，因此倒装芯片在组装和操作期间的机械完整性成为问题。为了克服这个问题，在芯片和衬底之间引入了刚性密封剂（底部填充）。这减少了有效的CTE失配，并减少了焊料互连所承受的有效应力。底部填充的存在显着提高了长期可靠性。但是，底部填充材料确实会在硅芯片中引入高水平的机械应力。组装中的应力是组装过程，底部填充材料和底部填充固化过程的函数。因此，底部填充材料的选择和处理对于实现所需的性能和可靠性至关重要。以前的出版物中介绍了底部填充材料对固化期间倒装芯片组件中引起的机械应力的影响。本文研究了固化参数对选定的商用底部填充材料的影响，并将这些特性与倒装芯片组件在加工过程中产生的应力相关联。

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