Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio

Shyam Akashe; Sanjay Sharma

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Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio

机译：考虑纳米尺度技术和晶体管比率的具有SRAM单元设计材料参数的低功耗高静态噪声裕量

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This paper presents the comprehensive summary of low power 7T SRAM cell design with power reduction in both active and standby mode. This paper proposes 7T SRAM cell structure which has no direct path through BL to data storage node, so this cell structure has higher forbearance against external noise in this way it can retain exact data at storage node. As we are using 45 nm technology for 7T SRAM cell design we can reduce size by great extent. In proposed 7T SRAM cell design, transistors are arranged in such a manner by which data destruction never occurs in the read operation. The simulation result shows that Static Noise Margin (SNM) of proposed 7T SRAM cell design is enhanced compare to other existing designs. Various operating parameter are also calculated for proposed 7T SRAM cell.

机译：本文介绍了低功耗7T SRAM单元设计的全面总结，该设计在工作和待机模式下均降低了功耗。本文提出了一种7T SRAM单元结构，该结构没有直接通过BL到达数据存储节点的路径，因此这种单元结构具有更高的抵御外部噪声的能力，从而可以在存储节点上保留准确的数据。由于我们将45 nm技术用于7T SRAM单元设计，因此可以在很大程度上减小尺寸。在提出的7T SRAM单元设计中，晶体管的排列方式使得在读取操作中不会发生数据破坏。仿真结果表明，与其他现有设计相比，拟议的7T SRAM单元设计的静态噪声容限（SNM）有所增强。还针对建议的7T SRAM单元计算了各种工作参数。

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《Quantum Matter》 |2013年第1期|共4页
作者
Shyam Akashe; Sanjay Sharma;
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正文语种 eng
中图分类计量学;
关键词
SRAM; Static Noise Margin (SNM); Low Power; Leakage Current; Operating Parameter; CMOS;

机译：SRAM;静态噪声裕量（SNM）;低功耗;漏电流;工作参数;CMOS;

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1. Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio [J] . Shyam Akashe, Sanjay Sharma Quantum Matter . 2013,第1期

机译：考虑纳米尺度技术和晶体管比率的具有SRAM单元设计材料参数的低功耗高静态噪声裕量
2. Static Noise Margin Analysis during Read Operation of 7T SRAM Cells in 45nm Technology for Increase Cell Stability [J] . Shelendra Singh Tomar, Madhav Singh, Shyam Akashe International Journal of Engineering Science and Technology . 2011,第9期

机译：使用45nm技术对7T SRAM单元进行读取操作期间的静态噪声裕度分析，以提高单元稳定性
3. Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices [J] . Kumar Harekrishna, Tomar V. K. Journal of circuits, systems and computers . 2021,第6期

机译：用于超低功耗设备的扩展噪声裕度亚斯雷姆电池的低功率设计
4. Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin [C] . Chandrabhan Kushwah, Santosh K. Vishvakarma International symposium on progress in VLSI design and test . 2012

机译：超低功耗亚阈值SRAM单元设计可改善读取静态噪声裕度
5. High performance, high stability and low power SRAM design by using carbon nanotube field effect transistors. [D] . Wang, Wei. 2012

机译：使用碳纳米管场效应晶体管的高性能，高稳定性和低功耗SRAM设计。
6. Power optimized variation aware dual-threshold SRAM cell design technique [O] . Aminul Islam, Mohd Hasan 2011

机译：功耗优化的变化感知双阈值SRAM单元设计技术
7. Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors [O] . Yiming Li, Chih-Hong Hwang, Shao-Ming Yu 2007

机译：具有32nm Fin键盘型晶体管的六晶体管静态随机存取存储器静态噪声裕度的数值模拟

Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio

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