首页>
外国专利>
WAFER LEVEL CHIP SCALE PACKAGE, STACKED PACKAGE THEREOF, AND FABRICATING METHOD THEREOF TO REDUCE THICKNESS OF SEMICONDUCTOR CHIP AND MAINTAIN INTENSITY OF CHIP SCALE PACKAGE
WAFER LEVEL CHIP SCALE PACKAGE, STACKED PACKAGE THEREOF, AND FABRICATING METHOD THEREOF TO REDUCE THICKNESS OF SEMICONDUCTOR CHIP AND MAINTAIN INTENSITY OF CHIP SCALE PACKAGE
展开▼
机译：晶片级芯片包装，其中的堆叠式包装及其制造方法，以降低半导体芯片的厚度和芯片包装的主要强度
展开▼
页面导航
摘要
著录项
相似文献
摘要
PURPOSE: A wafer level chip scale package, a stacked package thereof, and a fabricating method thereof are provided to reduce thickness of a semiconductor chip and maintain intensity of a chip scale package by adhering a wiring substrate on a back side of the semiconductor chip. CONSTITUTION: A semiconductor chip(34) includes an active side and a back side opposite to the active side. A plurality of chip pads(31) are formed on the active side. A via(37) is formed on the chip pad. An insulating layer(38) is formed on an inner side of the via. A plug(50) is formed in the inside of the via and is electrically connected to the chip pad. A wiring substrate is adhered on the back side of the semiconductor chip. A substrate pad(45) is formed on an upper face of the wiring substrate. The substrate pad is electrically connected to the plug. A connection pad(47) is formed on a lower face of the wiring substrate opposite to the upper face of the wiring substrate. The connection pad is electrically connected to the substrate pad.
展开▼
