Carbon Nanotube Vias for Multilevel Interconnects Using CMP Techniques

机译：使用CMP技术的多层互连碳纳米管通孔

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We have developed carbon nanotube (CNT) vias using thermal chemical vapor deposition (CVD) at a growth temperature of 450℃ with cobalt catalysts, titanium carbide ohmic contacts, and tantalum barrier layers on copper wiring. The total resistance of the CNT via comprised of about 1,000 tubes, was three orders of magnitude lower than that of one CNT, indicating that the current flows in parallel, through the tubes. We have also demonstrated a mechanical polishing technique for CNT vias. The 1-μm-high out-projecting CNTs were polished using a diamond slurry of 30-μm-diameter particles mixed in oil at pressures below 18 kPa. Because the adhesion strength of the CNTs was about 5.5 MPa, the CNT vias were able to withstand the mechanical stress applied during the polishing process.

机译：我们已经开发了一种碳纳米管（CNT）通孔，它使用热化学气相沉积（CVD）在450℃的生长温度下与钴催化剂，碳化钛欧姆接触和铜布线上的钽阻挡层结合在一起。 CNT通孔的总电阻由约1,000个管组成，比一个CNT的总电阻低三个数量级，表明电流并行流过这些管。我们还展示了CNT通孔的机械抛光技术。使用直径为30μm的颗粒的金刚石浆液在低于18 kPa的压力下混合在油中，对1μm高的突出碳纳米管进行抛光。由于CNT的粘合强度约为5.5 MPa，因此CNT通孔能够承受抛光过程中施加的机械应力。

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《CMP-MIC Catalog no.05 IMIC - 1000P; International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference(CMP-MIC); 20050223-25; Fremont,CA(US)》|2005年|P.527-534|共8页
会议地点 FremontCA(US)
作者
Mizuhisa Nihei; Akio Kawabata; Shintaro Sato; Daiyu Kondo; Masahiro Horibe; Hiroki Shioya; Taisuke Iwai; Yuji Awano;
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Fujitsu Limited, 10-1, Morinosato-Wakamiya, Atsugi 243-0197, Japan;

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原文格式 PDF
正文语种 eng
中图分类 TM23;
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2. Carbon nanotube array vias for interconnect applications [J] . Jyh-Hua Ting, Ching-Chieh Chiu, Fuang-Yuan Huang Journal of Vacuum Science & Technology . 2009,第3期

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3. Understanding the Impact of Inductance in Carbon Nanotube Bundles for VLSI Interconnect Using Scalable Modeling Techniques [J] . Nieuwoudt A., Massoud Y. IEEE transactions on nanotechnology . 2006,第期

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4. Carbon Nanotube Vias for Multilevel Interconnects Using CMP Techniques [C] . Mizuhisa Nihei, Akio Kawabata, Shintaro Sato, International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference . 2005

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5. High-frequency impedance extraction of interconnects considering substrate effects and exploration of single-walled carbon nanotubes for future VLSI interconnects. [D] . Srivastava, Navin. 2009

机译：考虑衬底效应的互连线的高频阻抗提取和用于未来VLSI互连线的单壁碳纳米管的探索。
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7. Carbon nanotube array vias for interconnect applications [O] . Ting, J. -H., Chiu, C. -C., Huang, F. -Y. 2007

机译：用于互连应用的碳纳米管阵列通孔

Carbon Nanotube Vias for Multilevel Interconnects Using CMP Techniques

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