• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Conference on Challenges in Process Integration and Device Technology 18-19 September 2000 Santa Clara, USA >Yield-limiting NMOSFET gate depletion in a deep sub-micron CMOS process
【24h】

Yield-limiting NMOSFET gate depletion in a deep sub-micron CMOS process

机译：在深亚微米CMOS工艺中限制产量的NMOSFET栅极耗尽

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Bitmap and electrical microprobe techniques were employed to detect and isolate NMOS gate depletion within the SRAM cells of our 0.20umm Complementary Poly CMOS process. This gate depletion problem led to 1 3C drop-off in device drive current and about a 300mV increase in threshold voltage. These shifts in device performance produced massive circuit failures within memory circuits and zero yield at wafer probe. Experiments were performed towards conclusively identifying and resolving this gate depletion failure mechanism. Several process modifications were implemented towards eliminating the NMOS gate depletion problem without compromising our margin against PMOS boron penetration. These process improvements led to dramatic increases in probe yield.
机译：位图和电子探针技术被用于检测和隔离我们0.20umm互补多晶硅CMOS工艺的SRAM单元中的NMOS栅极耗尽。此栅极耗尽问题导致器件驱动电流下降1 3C，阈值电压增加约300mV。器件性能的这些变化导致存储电路内部发生大量电路故障，晶圆探针的成品率降至零。进行了实验以最终确定并解决该栅极耗尽失效机制。为了消除NMOS栅极耗尽问题而进行了几项工艺修改，而又不损害我们抵抗PMOS硼渗透的余地。这些过程的改进导致探针产量的显着提高。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号