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首页> 外文会议>Electrochemical Society(ECS) Meeting;International Symposium on Silicon-on-Insulator Technology and Devices; 20070506-11;20070506-11; Chicago,IL(US);Chicago,IL(US) >Physics and Integration Of Fully-Depleted Silicon-On-Insulator Devices
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Physics and Integration Of Fully-Depleted Silicon-On-Insulator Devices

机译：完全耗尽的绝缘体上硅器件的物理和集成

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摘要

This paper gives an overview of the device physics and the process integration challenges of fully-depleted (FD) silicon-on-insulator (SOI) devices for advanced technology nodes. In the first part of the presentation, the physics related to the operation of ultra-thin film devices is described as well as how device scaling is impacted by the device parameters. Next, major fabrication challenges faced by fully-depleted SOI devices are reviewed along with their most recent progress. The technology modules reviewed include isolation, substrate engineering (limits of ultra-thin layers, strained layers, buried insulator materials,...), gate stack (high k and gate workfunction engineering techniques), methods for reducing SD parasitic resistance, such as elevated source/drain, as well as stress techniques.
机译：本文概述了用于高级技术节点的全耗尽（FD）绝缘体上硅（SOI）器件的器件物理以及工艺集成挑战。在演示的第一部分中，描述了与超薄膜设备的操作有关的物理学以及设备参数如何影响设备缩放。接下来，将对SOI器件完全耗尽所面临的主要制造挑战及其最新进展进行回顾。审查的技术模块包括隔离，衬底工程（超薄层，应变层，埋入绝缘体材料的限制等），栅极堆叠（高k和栅极功函数工程技术），降低SD寄生电阻的方法，例如高的源/漏以及应力技术。

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