DRAM TECHNOLOGY FOR 100NM AND BEYOND

机译：100NM及以后的DRAM技术

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The key challenges for scaling of DRAM cells are reviewed for trench capacitor cells and stacked capacitor cells. Both cell types have to implement significant innovations for 100nm and beyond. Cell layout/design have to be innovated for both cell types. New materials have to be introduced like high-k materials for capacitor, W/WN gates for gate resistance reduction and low-k materials for reduced parasitic capacitance. Transistor construction is another key element in scaling. Patterning, especially lithographic techniques, have to be significantly improved. This paper gives an overview on DRAM roadmap for both cell technologies. The viability of trench technology down to 70nm is demonstrated.

机译：对于沟槽电容器单元和堆叠电容器单元，对DRAM单元的缩放的关键挑战进行了综述。两种类型的电池都必须在100nm及以上工艺上实现重大创新。两种电池类型的电池布局/设计都必须创新。必须引入新材料，例如用于电容器的高k材料，用于降低栅极电阻的W / WN栅极和用于减小寄生电容的低k材料。晶体管构造是缩放的另一个关键要素。图案化，尤其是光刻技术，必须得到显着改善。本文概述了两种单元技术的DRAM路线图。演示了沟槽技术的可行性，该技术可低至70nm。

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来源
《Electrochemical Society Meeting and International Symposium on ULSI Process Integration III; 20030428-20030502; Paris; FR》|2003年|P.123-132|共10页
会议地点 Paris(FR);Paris(FR)
作者
K. H. Kuesters; J. Alsmeier; J. Faul; J. Luetzen; T. Zell;
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作者单位

Memory Development Center (MDC), Infineon Technologies P.O. Box 100940, D 01076 Dresden, Germany;

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原文格式 PDF
正文语种 eng
中图分类大规模集成电路、超大规模集成电路;
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1. Performance of ArF Resist Process for 100nm DRAM Full Chip [J] . Ki-Soo Shin, Hyeong Soo Kim, Jae Chang Jung Journal of Photopolymer Science and Technology . 2002,第3期

机译：100nm DRAM全芯片ArF抵抗工艺的性能
2. A 100nm node CMOS technology for practical SOC application [J] . Atsuki Ono, Katsuhiko Fukasaku, Tomohiro Hirai, 電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials . 2001,第573期

机译：适用于实际SOC应用的100nm节点CMOS技术
3. A 100nm node CMOS technology for practical SOC application [J] . Atsuki Ono, Katsuhiko Fukasaku, Tomohiro Hirai, 電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials . 2001,第573期

机译：一个100nm节点CMOS技术，用于实际SOC应用
4. COB stack DRAM cell technology beyond 100nm technology node (invited paper) [C] . Yongjik Park, Kinam Kim International Electron Devices Meeting . 2001

机译：COB堆栈DRAM Cell技术超出100nm技术节点（邀请纸）
5. Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service. [D] . Tran, Le-Nguyen. 2013

机译：DRAM / eDRAM和3D-DRAM的省电方法，利用工艺变化，温度变化，设备降级和内存访问工作负载变化，以及使用具有服务质量的3D-DRAM的创新的异构存储管理方法。
6. A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors [O] . Woo Young Choi, Gyuhan Yoon, Woo Young Chung, 2019

机译：基于技术-计算机辅助设计的DRAM存储电容器可靠性预测模型
7. Performance of ArF Resist Process for 100nm DRAM Full Chip. [O] . Ki-Soo Shin, Hyeong Soo Kim, Jae Chang Jung 2002

机译：ARF抗蚀剂的性能100nm DRAM全芯片。

DRAM TECHNOLOGY FOR 100NM AND BEYOND

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