Active Silicon Interposer for Heterogeneous Integration: System Scaling and Cost Effectiveness

机译：异构集成的有源硅中介层：系统扩展和成本效益

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摘要

Achieved system scaling by implementing key system functions into active interposer. Demonstrated partitioning of System on Chip (SoC) to smaller dies to achieve lower cost and higher yield. Heterogeneous integration involving 130 nm active silicon interposer, 65 nm split I/O chip and 28 nm FPGA die is demonstrated. A cost model was developed for this integration approach and it confirmed that the system scaling and cost reduction is higher for advanced nodes.

机译：通过将关键的系统功能实现到活动插入器中，实现了系统扩展。演示了将片上系统（SoC）划分为较小的芯片，以实现更低的成本和更高的良率。演示了涉及130 nm有源硅中介层，65 nm拆分I / O芯片和28 nm FPGA芯片的异构集成。为此集成方法开发了一种成本模型，它证实了高级节点的系统扩展和成本降低更高。

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来源
《2019 Electron Devices Technology and Manufacturing Conference》|2019年|339-341|共3页
会议地点 Singapore(SG)
作者
Vivek Chidambaram; Jayabalan Jayasanker; Sharon Lim Pei Siang; Wang Xiang Yu; V. N. Sekhar; Surya Bhattacharya;
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作者单位

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Through-silicon vias; Reliability; Field programmable gate arrays; Silicon; Bonding; Electrostatic discharges;

机译：硅通孔;可靠性;现场可编程门阵列;硅;键合;静电放电;;

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专利

1. Silicon Interposer Package for MMIC Heterogeneous Integration Based on Gold/Solder Ball Flip-Chip Technique [J] . Yongrong Shi, Dengyun Shao, Wenjie Feng, Components, Packaging and Manufacturing Technology, IEEE Transactions on . 2019,第8期

机译：基于金/锡球倒装芯片技术的MMIC异构集成的硅中介层封装
2. Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems [J] . Kuttappa Ragh, Taskin Baris, Lerner Scott, Circuits and Systems I: Regular Papers, IEEE Transactions on . 2021,第4期

机译：用于多模系统的活性硅插入器的谐振时钟同步
3. An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems [J] . Ding Qian, Knight Graham, Mak Terrence IEEE transactions on very large scale integration (VLSI) systems . 2020,第9期

机译：具有用于许多核心系统的低功率混合无线有线时钟分配网络的活性硅插入器
4. Active Silicon Interposer for Heterogeneous Integration: System Scaling and Cost Effectiveness [C] . Vivek Chidambaram, Jayabalan Jayasanker, Sharon Lim Pei Siang, Electron Devices Technology and Manufacturing Conference . 2019

机译：非均相集成的活性硅插入：系统缩放和成本效益
5. Cervical Cancer in Low-Income Settings: Costs, Cost-effectiveness, and Budget Impact of Integrating Screening and Treatment into Existing Health Systems in East Africa [D] . Vodicka, Elisabeth. 2018

机译：低收入地区的宫颈癌：将筛查和治疗纳入东非现有卫生系统的费用，成本效益和预算影响
6. Large-Scale Clinical Systems. Large Scale Integrated Ambulatory Care Systems: Integration of Heterogeneous Systems into a Patient Information Network [O] . Karen K. Ellis 1990

机译：大型临床系统。大型综合门诊医疗系统：将异构系统集成到患者信息网络中
7. Heterogeneous System Level Integration Using Active Si Interposer [O] . Vivek Chidambaram, Sharon Lim Pei Siang, Wang Xiangyu, 2019

机译：异构系统级集成使用活性SI插入器

Active Silicon Interposer for Heterogeneous Integration: System Scaling and Cost Effectiveness

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