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Innovating SRAM design and test program for fast process-related defect recognition and failure analysis

机译:创新的SRAM设计和测试程序,可快速进行与过程相关的缺陷识别和故障分析

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Abstract: A special SRAM has been designed as a yield enhancement vehicle in a 0.35 micrometer CMOS technology. Extra design rules were added to encourage process defects on certain places and discourage them on others. From the failure signature of a memory cell (0 or 1 failure) and its failure extent (single cell, double cell, bitline, wordline, ...) one can uniquely determine the process related cause of the failure. A dedicated test program has been developed to find the most common failures in a memory cell (e.g. floating bitline, bitline shorted to ground or Vdd, shorts between the nodes of the cell, ...). The innovating characteristics of the design allow to link these failures in an SRAM with high probability to a process related defect and its location within the memory cell. By simply testing the SRAM the main cause of failure can be found which can help to drive yield improvement, without doing intensive failure analysis. In this paper the design philosophy and the test methodology of this SRAM are described, illustrated with some examples of process related defects that proved the usefulness and the strength of the design and the test program. !11
机译:摘要:一种特殊的SRAM已被设计为采用0.35微米CMOS技术的良率提高工具。添加了额外的设计规则,以鼓励某些地方的工艺缺陷并阻止其他地方的缺陷。根据存储单元的故障特征(0或1故障)及其故障程度(单单元,双单元,位线,字线等),可以唯一确定与过程相关的故障原因。已经开发出专用的测试程序来发现存储器单元中最常见的故障(例如,浮动位线,对地短路的位线或Vdd,单元节点之间的短路...)。设计的创新特性允许将SRAM中的这些故障以高概率链接到与过程相关的缺陷及其在存储单元中的位置。通过简单地测试SRAM,可以找到故障的主要原因,这可以帮助提高良率,而无需进行大量的故障分析。本文描述了该SRAM的设计原理和测试方法,并举例说明了一些与过程有关的缺陷,这些缺陷证明了设计和测试程序的有用性和强度。 !11

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