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Electroplating of Low Resistivity Copper Interconnection Layer for 60 nm Node

机译：60 nm节点的低电阻率铜互连层的电镀

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摘要

Quantitative measurement of resistivity is performed in a thin electroplated copper layer. A average resistivity of 2.6 μΩ/cm is obtained in a 600-nm-thick copper layer deposited by conventional electroplating on tantalum-nitride (TaN) barrier layer. This resistivity increases rapidly with decreasing thickness and reaches 12 μΩ/cm at a thickness of 20 nm. In 60 nm wide copper Damascene lines, the electroplating on the sidewall of copper seed layer nucleates 15 nm thick copper layers. Therefore, reduction of resistivity in such thin nucleated layer is important. The reduction of this layer can be achieved by the homogenous nucleation of the electroplating. This improvement is possible by various process parameters. Resistivity decreases to 6.0μΩ/cm in 20 nm thick copper layer in uniformly nucleated layer. It can be expected the manufacturing of the high-speed log LSI's with employing this interconnection.
机译：在薄电镀铜层中进行电阻率的定量测量。在含钽 - 氮化物（TAN）阻挡层上的常规电镀沉积的600nm厚的铜层中，获得平均电阻率为2.6μΩ/ cm。这种电阻率随着厚度的降低而迅速增加，厚度为20nm的12μΩ/ cm。在60 nm宽的铜镶嵌线中，电镀在铜种子层的侧壁上成核15nm厚的铜层。因此，这种薄成核层中的电阻率的降低是重要的。通过电镀的均匀成核来实现该层的减少。各种过程参数可以实现这种改进。电阻率在均匀核化层中在20nm厚的铜层中降低至6.0μΩ/ cm。可以预期使用该互连的高速记录LSI的制造。

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