Algorithms and architectures for performing modular multiplication operations are important in cryptography and Residue Number System. In this paper Montgomery's algorithm has been broken into two concurrent no-interleaved multiplication operations. The architectures derived from this algorithm are systolic and need near communication links only. Thus, very well suited for VLSI implementation. The presented architectures offer a great flexibility of finding the best trade-off between hardware cost and throughput rate by changing the digit size.
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