A model has been developed to predict the yield of flip-chip solder assemblies based on calculated solder shapes. It is a physical model considering a limited number of physical factors such as the mean and the standard deviation of the solder volume distribution, the assembly warpage, the die size, and the number of inputs/outputs (I/O's). The main features of the model are: (1) the quick calculation of the solder height of every solder joint out of hundreds or thousands of connections; (2) the definition of failure criteria to determine the assembly yield. The quick calculation is accomplished by the use of a force model to estimate molten solder's normal reaction force corresponding to the solder's height, volume, circular pad diameter and surface tension coefficient. The failure criteria are height limits determined using surface evolver, which is a public tool for solder shape estimation. Outside the height limits, it is difficult to achieve convergent solutions; therefore, the limits are chosen as failure criteria since they implied large potential manufacturing variations in solder shapes. To illustrate the modeling capability, a case with 1 cm/spl times/1 cm chip, 1024 I/O's is studied. The model shows that a standard deviation of 25% for 4.48 e/sup -7/ cm/sup 3/ mean solder volume produces low yields. The variance of 19% for 4.48 e/sup -7/ cm/sup 3/ is required for a 100% yield.
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机译：已经开发了一个模型，可以根据计算出的焊料形状来预测倒装芯片焊料组件的成品率。它是一个物理模型，考虑了有限数量的物理因素，例如焊料量分布的平均值和标准偏差，装配翘曲，管芯尺寸和输入/输出（I / O）数。该模型的主要特点是：（1）快速计算出数百个或数千个连接中每个焊点的焊锡高度； （2）定义失效准则，确定装配合格率。快速计算是通过使用力模型来完成的，该模型用于估计与焊料的高度，体积，圆形焊盘直径和表面张力系数相对应的熔融焊料的法向反作用力。失效标准是使用表面演化器确定的高度极限，表面演化器是用于评估焊料形状的公共工具。超出高度限制，很难实现收敛的解决方案。因此，选择这些极限作为失效标准，因为它们暗示了焊料形状在制造方面的巨大潜在差异。为了说明建模能力，研究了一个1 cm / spl次/ 1 cm芯片，1024个I / O的情况。该模型显示，对于4.48 e / sup -7 / cm / sup 3 /平均焊料量，标准偏差为25％时，成品率较低。 100％的产量要求4.48 e / sup -7 / cm / sup 3 /的方差为19％。
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